The present invention is generally directed to analog circuits that are fabricated using small feature-sized MOSFET processes and, in particular, to a circuit that reduces sub-threshold leakage currents in small MOSFET devices connected to sensitive analog circuit nodes.
As the feature size of MOSFET processes shrink, the MOSFET sub-threshold drain-to-source leakage current when the transistor is supposedly turned off becomes increasingly large. In analog circuits where it is critical for a node to stay at high impedance, this increased leakage current may no longer be ignored. When the devices connected to the high impedance node draw large enough leakage currents, the performance of the circuit may suffer significantly. For instance, in a phase-locked loop (PLL), the devices connected to the high-impedance node of the loop filter may draw enough current when the devices are supposedly off to cause jitter in the PLL output.
Therefore, there is a need in the art for improved analog circuits that are fabricated using small feature-sized MOSFET processes. In particular, there is a need for circuits that reduce the sub-threshold leakage currents in small MOSFET devices connected to sensitive analog circuit nodes.
Low leakage current versions of three commonly used analog switches are shown to demonstrate techniques of reducing MOSFET sub-threshold leakage currents which can be significant in modern small-feature-sized CMOS processes. These circuits may be coupled to the high-impedance node of a phase-locked loop (PLL), for example. The three circuits include 1) pull-up/pull-down devices, 2) a pre-charge circuit, and 3) a transmission switch (T-switch) for analog testing. It should be noted that the low leakage current designs disclosed herein are general purpose and are not necessarily limited to PLL designs.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use with an operational circuit having a high impedance node, a pre-charge circuit capable of pre-charging the high-impedance node to a target voltage when a pre-charge signal driving the pre-charge circuit is enabled. According to an advantageous embodiment of the present invention, the pre-charge circuit comprises: 1) a charge voltage circuit capable of charging an internal common node of the pre-charge circuit to the target voltage when the pre-charge signal is enabled; 2) a transmission gate switch capable of coupling the internal node to the high-impedance node when the pre-charge signal is enabled, the transmission gate switch comprising a first N-channel transistor having a drain coupled to the high-impedance node, a gate coupled to a Logic 1 when the pre-charge signal is enabled, and a source coupled to the internal common node; and 3) a gate-biasing circuit driven by the pre-charge signal, wherein the gate-biasing circuit is off when the pre-charge signal is enabled and generates a negative Vgs bias on the first N-channel transistor when the pre-charge signal is disabled.
According to one embodiment of the present invention, the transmission gate switch further comprises a first P-channel transistor having a drain coupled to the high-impedance node, a gate coupled to a Logic 0 when the pre-charge signal is enabled, and a source coupled to the internal common node.
According to another embodiment of the present invention, the gate-biasing circuit generates a positive Vgs bias on the first P-channel transistor when the pre-charge signal is disabled.
According to still another embodiment of the present invention, the gate of the first N-channel transistor is coupled to a Logic 0 when the pre-charge signal is disabled and the gate-biasing circuit holds the internal common node at a voltage higher than Logic 0 to thereby generate the negative Vgs bias on the first N-channel transistor when the pre-charge signal is disabled.
According to yet another embodiment of the present invention, the gate of the first P-channel transistor is coupled to a Logic 1 when the pre-charge signal is disabled and the gate-biasing circuit holds the internal common node at a voltage less than Logic 1 to thereby generate the positive Vgs bias on the first P-channel transistor when the pre-charge signal is disabled.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to is or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation. A controller may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with a controller may be, centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.